Senior Digital IC Verification Consultant

Full time/ Duration: 12 months

Slået op: 08.04.2025

Start Date: May 1st

Work Mode: Onsite

Tools Used in Our Project

• Simulator: Synopsys VCS
• Formal verification: VC Formal
• Coverage closure: Hierarchical Verification Plan
• Debugging: Verdi
• Version control: Git

Relevant Skills Required

• Language: Verilog/System Verilog (UVM is a plus)
• Scripting/Modeling: Python/SystemC/TCL/Makefiles

Skills

• Metric driven functional verification (functional coverage closure and code coverage closure)
• SV assertion
• SystemVerilog Testbench implementation
• Test implementation in TCL
• Coverage model implementation
• Reference model implementation

Description 

Capax is seeking an experienced freelancer on behalf of our client to take on the role of Senior Digital IC Verification Consultant. You will be working onsite and making a significant impact in the technology sector by ensuring the integrity and performance of digital integrated circuits through rigorous verification processes. You will be part of a small team focused on high-value deliveries that are central to the company’s strategy. As a Senior Consultant, you will be involved in analyzing and refining the requirements for proposed features, collaborating closely with your team, and ultimately developing solutions that meet these requirements. The role primarily involves ensuring the integrity and performance of digital integrated circuits through rigorous verification processes.

Responsibilities 

Develop and implement verification plans and testbenches using SystemVerilog and UVM. Perform metric-driven verification to ensure functional and code coverage closure. Utilize advanced debugging tools to identify and resolve issues. Collaborate with cross-functional teams to define verification strategies and methodologies. Implement and maintain coverage and reference models.

Qualifications 

Proficiency in Verilog/System Verilog and scripting languages such as Python, SystemC, TCL, and Makefiles. Extensive experience with Synopsys VCS, VC Formal, Verdi, and Git. Strong understanding of metric-driven functional verification and SV assertion. Proven track record in SystemVerilog Testbench implementation and test development. Excellent problem-solving skills and attention to detail.

Contact

This recruitment is assisted by Capax Recruitment. For more information about the position, please contact Xenia at xrr@capax.dk.